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Get Static Timing Analysis for Nanometer Designs Here A Practical Approach

Static Timing Analysis for Nanometer Designs book covers topics resembling cell timing and power modeling; interconnect modeling and evaluation, delay calculation, crosstalk, noise and the chip timing verification using static timing analysis. For each of these topics, the book offers a theoretical background in addition to detailed examples to elaborate the concepts.

The static timing analysis subjects coated begin from verification of simple blocks helpful for a newbie to this field. The topics then lengthen to complex nanometer designs with in-depth therapy of ideas resembling modeling of on-chip variation, clock gating, half-cycle paths, in addition to timing of supply-synchronous interfaces equivalent to DDR. The affect of crosstalk on timing and noise is roofed as is the utilization of hierarchical design methodology.

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